Process Statement in VHDL

VHDL Programming

Process Statement :

In an architecture for an entity, all statements are concurrent. So where do sequential statements exist in VHDL ?  There is a statement called the process statement that contains only sequential statements. The process statement is itself a concurrent statement. A process statement can exist in an architecture and define regions in the architecture where all statements are sequential.

A process statement has a declaration section and a statement part. In the declaration section, types, variables, constants, subprograms, and so on can be declared. The statement part contains only sequential statements. Sequential statements consist of CASE statements, IF THEN ELSE statements, LOOP statements, and so on.

Process Example :

This is an example of a process statement.

Following is a model of a two-input NAND gate:


This example shows how to write a model for a simple two-input NAND gate using a process statement. The USE statement declares a VHDL package that provides the necessary information to allow modeling this NAND gate with 9 state logic. The USE statement was included so that the model could be simulated with a VHDL simulator without any modifications. The entity declares three ports for the nand2 gate. Ports a and b are the inputs to the nand2 gate and port c is the output. The name of the architecture is the same name as the entity name. This is legal and can save some of the headaches of trying to generate unique names.
The architecture contains only one statement, a concurrent process statement. The process declarative part starts at the keyword PROCESS and ends at the keyword BEGIN. The process statement part starts at the keyword BEGIN and ends at the keywords END PROCESS. The process declaration section declares a local variable named temp. The process statement part has two sequential statements in it; a variable assignment statement:


The process contains an explicit sensitivity list with two signals contained in it:


The process is sensitive to signals a and b. In this example, a and b are input ports to the model. Input ports create signals that can be used as inputs; output ports create signals that can be used as outputs; and in out ports create signals that can be used as both. Whenever port a or b has a change in value, the statements inside of the process are executed. Each statement is executed in serial order starting with the statement at the top of the process statement and working down to the bottom. After all of the statements have been executed once, the process waits for another change in a signal or port in its sensitivity list. The process declarative part declares one variable called temp. Its type is std_logic.



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