Hardware in VHDL

 VHDL Programming

VHDL Descriptions consist of primary design units and secondary design units. The primary design units are the Entity and the Package. The secondary design units are the Architecture and the Package Body. Secondary design units are always related to a primary design unit. Libraries are collections of primary and secondary design units. A typical design usually contains one or more libraries of design units.


Entity : 
A VHDL entity specifies the name of the entity, the ports of the entity, and entity-related information. All designs are created using one or more entities.

Let’s take a look at a simple entity example:

PORT ( a, b, c, d : IN BIT;
s0, s1 : IN BIT;
x, : OUT BIT);
END mux;


The keyword ENTITY signifies that this is the start of an entity statement. keywords of the language and types provided with the STANDARD package are shown in ALL CAPITAL letters. For instance, in the preceding example, the keywords are ENTITY, IS, PORT, IN, INOUT, and so on. The standard type provided is BIT. Names of user-created objects such as mux, in the example above, will be shown in lower case. The name of the entity is mux. The entity has seven ports in the PORT clause. Six ports are of mode IN and one port is of mode OUT. The four data input ports (a, b, c, d) are of type BIT. The two multiplexer select inputs, s0 and s1, are also of type BIT. The output port is of type BIT. The entity describes the interface to the outside world. It specifies the number of ports, the direction of the ports, and the type of the ports.


Architectures :

The entity describes the interface to the VHDL model. The architecture describes the underlying functionality of the entity and contains the statements that model the behavior of the entity. An architecture is always related to an entity and describes the behavior of that entity. An architecture for the counter device described earlier would look like this:


The keyword ARCHITECTURE signifies that this statement describes an architecture for an entity. The architecture name is dataflow. The entity the architecture is describing is called mux.


The reason for the connection between the architecture and the entity is that an entity can have multiple architectures describing the behavior of the entity. For instance, one architecture could be a behavioral description, and another could be a structural description. The textual area between the keyword ARCHITECTURE and the keyword
BEGIN is where local signals and components are declared for later use. In this example signal select is declared to be a local signal. The statement area of the architecture starts with the keyword BEGIN. All statements between the BEGIN and the END netlist statement are called concurrent statements, because all the statements execute concurrently.


Examine the first assignment statement from architecture behave, as
shown here:


A signal assignment is identified by the symbol <=. Signal select will get a numeric value assigned to it based on the values of s0 and s1. This statement is executed whenever either signal s0 or signal s1 has an event occur on it. An event on a signal is a change in the value of that signal. A signal assignment statement is said to be sensitive to changes on any signals that are to the right of the <= symbol. This signal assignment statement is sensitive to s0 and s1. The other signal assignment statement in architecture dataflow is sensitive to signal select.


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