VHDL – WAIT UNTIL Expression

 VHDL Programming

Wait statement : The statement that causes suspension of a procedure.

WAIT UNTIL Expression :

The WAIT UNTIL boolean_expression clause suspends execution of the process until the expression returns a value of true. This statement effectively creates an implicit sensitivity list of the signals used in the expression. When any of the signals in the expression have events occur upon them, the expression is evaluated. The expression must return a boolean type or the compiler complains. When the expression returns a true value, execution continues with the statement following the WAIT statement. Otherwise, the process continues to be suspended.

For example:


In this example, as long as the value of signal x is greater than or equal to 10, the WAIT statement suspends the process or subprogram. When the value of x is less than 10, execution continues with the statement following the WAIT statement.



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