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VLSI Based Final Year Projects 2013

VLSI Based Final Year Projects 2013 

 

  • A Lightweight Encryption Method Suitable For Copyright Protection
  • A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture
  • Concurrent Error Detection in Reed“SolomonEncoders and Decoders
  • VLSI Implementation of Multiplier-Free Low Power Baseband Filter for CDMA Systems
  • Reconfigurable Architecture for Network Flow Analysis
  • Processor and the Reconfigurable Logic on an FPGA
  • Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers
  • A Novel Multiplexer-Based Low-Power Full Adder
  • System Architecture and Implementation of MIMO Sphere Decoders on FPGA
  • Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays
  • A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
  • A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System
  • Blind Separation of Superimposed Shifted Images Using Parameterized Joint Diagonalization
  • Registers for Phase Difference Based Logic
  • Logical Reversibility of Computation
  • Efficient Communication Between the Embedded
  • A coding framework for low power address and data busses
  • Spread Spectrum Signaling for Speech Watermarking
  • The Reconfigurable Instruction Cell Array
  • Cost-Efficient SHA Hardware Accelerators
  • Fast Elliptic Curve Cryptography on FPGA

 



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