VLSI Based Project List

VLSI Based Project List


  1. An accumulator based compaction scheme for online BIST of RAMS (IEEE 2008)
  2. The reconfigurable instruction call array (IEEE 2008)
  3. Improving linear test data compression (IEEE 2006)
  4. Robust concurrent online testing of network on chip based on SOCS (IEEE 2008)
  5. Speed Referencing for continues hot rolling mill
  6. digital audio stenography
  7. Multi input and multi out for wireless communication system
  8. Weighted pseudo- random hybrid BIST (IEEE 2004)
  9. Low-power scan design using first level supply gating (IEEE 2005)
  10. Optimization techniques for FPGA based wave pipelined DSP blocks (IEEE 2005)
  11. A source synchronous double data rate parallel optical transciever ic (IEEE 2005)
  12. Registers for phase difference based logic (IEEE 2007)
  13. A combined gate replacement and input vector control approach for leakage current reduction (IEEE 2006)
  14. A high efficiency fully synchronous buck converter power delivery system based on finite state machine (IEEE 2006)
  15. X-masking during logic BIST and impact on defect coverage (IEEE 2006)
  16. New techniques for attestable fault identification in sequential circuits (IEEE 2006)
  17. Double sampling data checking technique an online testing solution for multi source noise induced errors on chip interconnects and buses (IEEE 2004)
  18. Leakage current reduction in CMOS circuit using ip vector control(IEEE 2004)
  19. VLSI based traffic light controller
  20. New and improved BIST diagnosis method combinatorial group testing theory (IEEE 2006)
  21. Energy management for battery power reconfigurable computing platforms (IEEE 2006)
  22. Design specific path delay testing in lookup table based FPGA (IEEE 2006)
  23. Exact and heuristic approaches to input vector control for leakage power reduction (IEEE 2006)
  24. Auto scan : A scan design without external scan input or output (IEEE 2005)
  25. A general purpose cell sequencer / Scheduler for ATM switches
  26. Wireless home appliances controller
  27. Characterization, Test and logic synthesis of Andor-Invertor (AOI)(IEEE 2005)
  28. FPGA implementation of scalable encryption algorithm (IEEE 2008)
  29. Low power design of precomputation based content addressable memory (IEEE 2008)
  30. Automatic constraint based test generation for behavioral HDL models (IEEE 2008)
  31. Event driven simulation of VLSI circuits
  32. A low-power multiplier with the spurious power suppression technique (IEEE 2007)
  33. Go/no- go testing of VCO modulation RF transceivers through the delayed-RF setup(IEEE 2007)
  34. A BIST TPG for low power dissipation and high fault coverage(IEEE 2007)
  35. Universal VLSI based on a redundant multiple valued sequential logic operation(IEEE 2007)
  36. A VHDL implementation of UART design with BIST capability(MALAYSAN JOURNAL 2006)
  37. Advanced encryption slandered (AES)
  38. Higher radix and redundancy factor for floating point SRT division (IEEE 2008)
  39. Diagnosis of logic circuits using compressed deterministic data and on chip response comparison (IEEE 2006)
  40. Extraction error modeling and automated model debugging in high performance custom design(IEEE 2006)
  41. Pipelined array based fir filter folding(IEEE 2005)
  42. On VLSI design of rank order filtering using DCRAM architecture (IEEE 2007)
  43. Speed control of DC motor
  44. Stepper motor controller
  45. Wireless camera controller
  46. A BIST circuit for DLL fault detection (IEEE 2008)
  47. Space vector modulation using VLSI(IEEE 2002)
  48. Variable run length coding for embedded progressive wavelet based image compression and decompression
  49. Hardware implementation of finger printing algorithm suited for digital cinema
  50. Finger printing reorganization
  51. Low power leading zero counting and anticipation logic for high speed floating point unit (IEEE 2008)
  52. Effective uses of FPGAS for brute force attack on RC4 ciphers (IEEE 2008)
  53. Efficient communication between the embedded processor and the reconfigurable logic on an FPGA (IEEE 2008)
  54. Hybrid type cam design for both power and performance efficiency (IEEE 2008)
  55. High speed VLSI architecture for parallel reed Solomon decoder
  56. A medium-grain reconfigurable for DSP VLSI design, benchmark mapping and performance (IEEE 2008)
  57. Area-efficient arithmetic expression evaluation using deeply pipelined floating-point cores (IEEE 2008)
  58. Automatic design of reconfigurable domain-specific flexible cores (IEEE 2008)
  59. Enhancement of fault injection techniques based on the modification of VHDL code (IEEE 2008)
  60. Diagnosis framework for locating failed segment of path delay faults (IEEE 2008)
  61. LFSR reseeding scheme achieving low power dissipation during test (IEEE 2008)



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